1. Field of Invention
Invention relates to digital video processing, particularly to semiconductor chip architecture and implementation of digital video compression and decompression.
2. Description of Background Art
Video data transmission requires wide bandwidth. If video data are stored and transferred in original format, recording medium with large capacity and transmission medium with wide bandwidth is needed. To obtain economic and efficient system for storing and transferring video data, video image generally needs to be compressed to reduce redundant and trivial information.
Since becoming international standard in 1994, MPEG-1/MPEG-2 has been adopted for many applications. As digitalization of video signal is increasingly more popular, and available bandwidth for handling large amount of data is seemingly always limited, MPEG technology provides general solution which has actually become common technology for coding digital video. There are many implementations of MPEG algorithm available, both in software and hardware. Software implementation of MPEG is generally more cost-effective than hardware implementation. While hardware implementation generally has better performance in real-time system.
Discrete Cosine Transform (DCT) and Inverse Discrete Cosine Transform (IDCT) refer to important video compression elements of MPEG standard. Hardware implementation of DCT/IDCT takes considerable amount of silicon design area. Speed of DCT/IDCT affects video system processing ability. Architecture of DCT/IDCT may compromise between area and processing speed determined by specific applications of chip. Since introduction of DCT/IDCT in 1970""s, much research has been performed on algorithms and designs for computing the DCT/IDCT.
Therefore, there is need for improved integrated chip design architecture and implementation for MPEG video codec application.
The invention resides in flexible VLSI (Very Large Scale Integration) architecture and implementation of video codec (coding/decoding) logic. Implementation of invention in VLSI is termed as Video Processing Unit (VPU). VPU operates in two modes: video encoding or decoding. In encoding mode, VPU receives digitized video input and compresses according to MPEG standard. In decoding mode, VPU receives MPEG video bitstream and decompresses according to MPEG standard. Supporting modules such as DRAM controller and motion estimation logic facilitate real-time MPEG codec processing. In particular, the invention presents a novel approach for implementing DCT and IDCT using the same hardware. The approach minimizes logic, while processing speed can meet MPEG MP@ML requirements. Preferably, there is no different set of logic for row and column processing.